High Density Fan-Out Panel Level Packaging of Multiple Dies Embedded in IC Substrates

Abstract

The ongoing roadmaps of miniaturization and functional heterogenity in electronics packaging are pushing the demand for advanced substrate technologies. In this paper we show the embedding in core cavity (EiCC) process running with $5 {\mu}{m} {L}/S$ and chips with $50 {\mu} m$ bump pitch. Two 6x6 mm2 dies are symmetrically embedded into an organic laminate matrix. A PCB core $( 100 {\mu} m$ thickness) with very low coefficient of thermal expansion (CTE) containing laser-cut cavities acts as a frame layer. Besides mechanical and handling stability the usage of such a frame offers the advantage of pre-integrating additional features like local fiducials, through vias or power lines by conventional PCB processes. Within that frame the dies are embedded by lamination of an organic build-up film. The chip contacts are then revealed in process based on plasma etching. After measuring chip positions the first redistribution layer (RDL) is formed in a semi-additive process (SAP) utilizing sputtering technique and adaptive laser direct imaging (LDI). Therefore, a newly developed LDI machine is used to write structures in $a7 {\mu} m$ photoresist. Subsequently a second RDL formation can be done. In this step high aspect ratio blind microvias with $20 {\mu} m$ diameter and up to $80 {\mu} m$ depth are drilled by UV-laser and filled in the following plating process. Altogether, with the combination of high density $5 {\mu} {m} {L}/S$ interconnects, high aspect ratio (2.5:1) blind microvias and $50 {\mu} m$ fine bump pitch on large panel formats we will give an outlook to upcoming challenges and possibilities in FO PLP.