Modeling, design and fabrication of ultra-thin and low CTE organic interposers at 40µm I/O pitch

Abstract

This paper presents a comprehensive study on the fundamental factors that impact the scalability of organic interposers to 40µm area array bump pitch, leading to the design and fabrication of ultra-thin and low CTE organic interposers at 40µm pitch. Silicon interposers were the first substrates used for 2.5D integration of logic and memory ICs at close proximity. However, the high cost and electrical loss of wafer back end of line (BEOL) silicon interposers has fueled the need for fine-pitch organic interposers. Organic substrates face two primary challenges in achieving finer I/O pitch: layer-to-layer mis-registration during copper-polymer re-distribution layer (RDL) fabrication due to the thermo-mechanical stability issue of organic laminate cores, and warpage during chip assembly on thin core substrates. This paper studies these two fundamental factors by finite element modeling (FEM) and experimental characterization, resulting in RDL design guidelines for low mis-registration and warpage. Reducing the copper thickness in each layer as well as the thickness of the polymer dielectric to below 10µm, resulted in significant reduction in CTE mismatch-induced stresses at different interfaces. The modeling-based design was verified by fabrication of a multi-layer RDL stack on 100µm thin low coefficient of thermal expansion (CTE) organic cores with ultra-thin build-up layers to achieve a bump pitch of 40µm. The assembly of chips on the thin organic interposer was optimized to minimize the warpage, leading to the demonstration of two-chip 2.5D organic interposers.