Abstract
Abstract In this study, we investigate the effects of dimensional scaling on device variation of back-end-of line (BEOL)- compatible ferroelectric field-effect transistor (FeFET) memory with amorphous oxide-semiconductor channel by considering random ferroelectric/dielectric (FE/DE) phase fluctuation. Our study based on TCAD simulation indicates that: i) For a given FE phase, scaling gate length not only improves memory window (MW) due to the sufficient ferroelectric switching during erase, but also increases MW variation (σMW), which is mainly dominated by high-voltage threshold (HVT) variation induced by erase operation. ii) For a given device size, reducing FE phase results in decreased MW with increased σMW. This σMW degradation could be suppressed at longer gate length due to the weak erase. iii) For gate width scaling, it has negligible effect on MW but induces the σMW increase, which could be ascribed to the increased probability of forming DE paths with larger grain-to-channel area ratio. Therefore, although scaling BEOL FeFET device size could increase MW, the increased σMW due to random FE/DE phase fluctuation may also need to be considered. These findings may provide insights for future FeFET design.
Published Version
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