Scalable Clustered Time Warp and Logic Simulation

Hervé Avril,Carl Tropper

doi:10.1155/1999/23047

Abstract

We introduce, in this paper, Clustered Time Warp (CTW), an algorithm for the parallel simulation of discrete event models on a general purpose distributed memory architecture. CTW has its roots in the problem of distributed logic simulation. It is a hybrid algorithm which makes use of Time Warp between clusters of LPs and a sequential algorithm within the clusters whereas Time Warp is traditionally implemented between individual LPs.We also develop a family of three checkpointing algorithms for use with CTW, each of which occupies a different point in the spectrum of possible trade-offs between memory usage and execution time. The algorithms were implemented and tested on several digital logic circuits and their speed, number of states saved and maximal memory consumption were compared to Time Warp. Our results showed that one of the algorithms saved an average of 40% of the maximal memory consumed by Time Warp while the other two decreased the maximal usage by 15 and 22%, respectively. The latter two algorithms exhibited a speed comparable to Time Warp, while the first algorithm was 60% slower.We investigated the scalability of CTW using 3 different queuing models and different service-time distributions and showed that the algorithm acts to limit the explosion of rollbacks exhibited by Time Warp. Furthermore, we showed that the memory requirements for CTW are three times smaller than that of Time Warp for one model and half as large for the two other models.

Highlights

A great deal of effort has gone into parallel logic simulation because reducing the time of uniprocessor simulators can have a significant impact on the design of VLSI systems
We evaluate the performance of Clustered Time Warp and its different checkpointing techniques introduced in the preceding section
The crossbar switch is a banyan network composed of 4 4 switch elements and is interfaced with each node by an AM2901 microprocessor whose purpose is to ensure the atomicity of memory operations performed on remotereferences

Summary

Introduction

A great deal of effort has gone into parallel logic simulation because reducing the time of uniprocessor simulators can have a significant impact on the design of VLSI systems. The simulation of these systems has, become a bottleneck in the overall design process [3] is an excellent survey of the work done in parallel logic simulation. "A Dynamic Loadbalancing Algorithm for Time Warp", IEEE Trans. [10] Groselj, B. and Tropper, C., "The Distributed Simulation of Clustered Processes", Distributed Computing, Springer Verlag, Vol IV, pp. D., "Processor Scheduling for Time Warp Parallel Simulation", Proc. D., "Processor Scheduling for Time Warp Parallel Simulation", Proc. 1991 SCS

Methods

Results

Conclusion