Scalable benchmark synthesis for performance evaluation of NoC core mapping

Abstract

Network On Chip is determined as an On-chip packet-switched communication in the study of multi-processors. As the number of components is proliferating, there were many issues regarding the performance of a network. By taking into consideration of this problem, in this paper, we proposed an efficient core mapping algorithm named BMAP, used for customizing the NoC platforms and performing the SPLASH-2 Benchmark synthesis evaluation. This proposed mapping technique is applied to various NoC applications and SPLASH-2 Benchmark applications. The experimental outcomes exhibit optimized NoC platforms on outperforming the performance and cost metrics when compared with other mapping algorithms. In contrast, the SPLASH-2 Benchmarks reveal that the proposed algorithm has a significant improvement in performance metrics against NMAP, MMAP, and EMAP algorithms. The metrics such as Speed-up Execution Time has improved by 40%, 30%, and 20%, and Latency reduced by 42%, 34%, and 28%, Energy efficiency was improved by 36%, 30%, 26%, and Power consumption reduced by 32.6%, 28.2%, and 26.4% respectively.