Performance evaluation of modified mesh-based NoC architecture

Abstract

With the advancement of technology in the field of VLSI, it is possible to integrate several computing elements onto a single chip. The performance of these single bus-based models still suffers from scalability on large-scale platforms. Therefore, network-on-chip (NoC) architecture integrating multiple cores in a single chip has emerged as an alternative. An efficient mapping is one of the most essential activities in high-performance multi-processor architectures. This research paper proposes an efficient core mapping and modified 2-D mesh NoC architecture. Every core is connected to the two routers via a network interface. In an efficient core mapping algorithm, the mapping region is selected based on Core Efficient Region (CER), which can improve the processor performance. The proposed core mapping algorithm is applied to the multimedia benchmarks. The experimental results show that the efficient core mapping algorithm outperforms the communication energy and performance when compared with other recent mapping algorithms.