Scalable and Dynamic Global Power Management for Multicore Chips

Abstract

The design for continuous computer performance is increasingly becoming limited by the exponential increase in the power consumption. In order to improve the energy efficiency of multicore chips, we propose a novel global power management technique. The goal of the technique is to deliver the maximum performance at a fixed power budget, without significant overhead. To tackle the exponential complexity of the power management for multiple cores, we apply a Reinforcement Learning technique, Q-learning, at the core level and then use a chip-level intelligent controller to optimize the power distribution among all cores. The power assignment adapts dynamically at runtime depending on the needs of the applications. The technique was evaluated using the PARSEC benchmark suite on a full system simulator. The experimental results show, in average, that with the proposed technique the overall performance is increased by 39% for a fixed power budget while the EDP is improved by 28%, compared to the non-DVFS baseline implementation.