Sampling plan optimization for CD control in low k 1 lithography

Abstract

For advanced process control, a sampling plan for critical dimension measurement is optimized through empirical considerations concerning the nature of error and a statistical approach. The metric of the optimization is the accuracy of lot mean estimation. In this work, critical dimension errors are classified into static and dynamic components. The static component is defined as the error which repeats through lots while keeping its tendency, and the dynamic as the error whose tendency changes by lot. In the basic concept of our sampling plan, sampling positions and size are determined from the static and dynamic error, respectively. The balance of sampling number of wafer, field and pattern is obtained under the restriction of total sampling size by a statistical theory with some assumptions. Based on the concept, we could make a sampling plan for 65 nm CMOS lithography.