Full chip gate CD error prediction for model-based OPC

Abstract

In this paper, a technique for full chip gate CD(critical dimension) error prediction based on empirical models will be presented and discussed. In order to be compatible with existing common terminologies, this technique can also be called model-based full chip gate CD verification, which has become an integral part of closed-loop design-to-silicon flow of gate layer masking processes at 90nm and 65nm technology nodes. The empirical optical-and-process models can be same or different (such as with defocus) from the ones which are widely used in model based OPC and ORC. Similar to but different from conventional ORC, which normally addresses the minimum feature check or fatal error check, the model-based gate CD verification technique will focus on CD error prediction and CD error distribution analysis for gate CD related yield improvement efforts. Current commercial ORC or model-based verification tools provide the capability of EPE (edge placement error) check and analysis, and with certain additional techniques they may also provide the capability of gate CD prediction or simulation for selected targets or figures. The new model-based gate CD verification technique will provide the capability of full chip CD error prediction and CD error distribution analysis for all concerned small gate CD targets.