Round busbar concept for 30 nH, 1.7 kV, 10 kA IGBT non-destructive short-circuit tester

Abstract

Design of a Non-Destructive Test (NDT) set-up for short-circuit tests of 1.7 kV, 1 kA IGBT modules is discussed in this paper. The test set-up allows achieving short-circuit current up to 10 kA. The important objective during the design of the test set-up is to minimize the parasitic inductance and assure equal current sharing among the parallel connected devices. Achieving of a low inductance level is very challenging due to the current and voltage ratings, the presence of series and parallel protection systems and the required access for a thermal camera. The parasitic extractor Ansys Q3D is used to estimate the parasitic inductances during the design. A new concept of round-shaped, low inductive busbars for an NDT set-up is proposed. Simulation results verified that both reduction of overall inductance and good uniformity in current sharing among parallel devices are achieved by utilizing a circular symmetry. Experimental validation of the simulation was performed using a preliminary set-up. Further, this concept can be implemented in the design of the busbars for the power converters, where the parallel connection of the switching devices is applied to obtain higher current levels. Introduction The Non-Destructive Test (NDT) is a cost-effective solution used to test high power semiconductor devices at the edges of their Safe Operating Areas (SOA). The presence of the protection circuit allows preventing the failure of the Device Under Test (DUT) at the occurrence of any possible instable behavior. Thus, a lot of tests can be performed without damaging of an expensive high power device [1]. Moreover, this technique allows making results independent of parametric variations among the different devices. During the design of an NDT for a very high current up to 10 kA, several aspects are needed to be taken into account. First, the stray inductance of the circuit provokes over/under voltages during transients and should, therefore, be minimized [2], [3]. The stray inductance also increases the turn-on time of the protection switches. Current and voltage ratings as well as the presence of series and parallel protections in the circuit are very challenging for achieving low inductance levels. Moreover, it is required by specification that during tests the temperature distribution inside the DUT is measured with an infrared camera. This puts physical limitations on the design of the busbars since an access for the infrared camera is required in order to monitor the temperature during heavy loadings. To minimize the inductance of the circuit, components with low stray inductances are used. Several components of the circuit are connected in parallel to obtain high current, so their equivalent inductance becomes low. To obtain a low inductive connection of the NDT circuit components, laminated busbars are used [4], [5]. In a busbar system, the copper plates are arranged in such a way that the currents in the nearby conductors flow in opposite directions forming as small flux producing surfaces as possible [6]. As the NDT is intended for a single-shot operation, the thickness of the conductive plates can be lower than in systems for continuous operation. However, the busbars are rather bulky due to the large dimensions of the high current and medium voltage components. Another important issue which has to be considered during the design of the busbars is equal current sharing among parallel devices required for such high current levels. During fast transients, unequal current distribution may lead to the damage of the devices experiencing a higher current than the other devices connected in parallel. In this paper the design of 10 kA-rated busbars having 30 nH stray inductance and providing a current imbalance lower than 7 % among the parallel components of the circuit is presented. The inductance and the current distribution of the busbars are estimated using Ansys Q3D [7] and experimentally validated thanks to a preliminary setup. Description of the NDT circuit The aim of an NDT equipment is to perform short-circuit tests in the presence of a protection circuit able to turn-off the current very quickly right after the test. This capability allows saving the DUT by limiting the energy dissipated on it. It also allows performing repetitive tests. Even in the possible case of a rupture of the device, this technique avoids explosions, making them possible for post-failure analysis. Fig. 1 shows a classical NDT experiment. Fig. 1: Electrical schematic of the NDT set-up with the commutation loops 1 and 2. B1, B2, B3, B4, B5, B6, B7 indicates the busbars. DUT – Device Under Test. The electrical schematic of the NDT with the commutation Loop 1 and Loop 2 is shown in Fig. 1. It includes the DUT, the series protection, parallel protection, load inductance Lload, DC link capacitance CDC, a high voltage power supply VDC, Schottky diodes, negative-voltage capacitance CNEG with corresponding negative voltage supply VNEG. There are two different short-circuits types: type 1 happens during the IGBT turn-on, while type 2 happens when the IGBT is at on-state. The NDT can provide both short-circuit types by different configuration and control timing schemes. The timing control schemes of the NDT are illustrated as shown in Fig. 2, in which high state means on-state and low state means off-state. For type 1 short-circuit, the load inductance in Fig. 1 should be removed. Before tests, series protection is on-state while parallel protection is off-state. During the tests, the DUT falls to shortcircuit, when it is triggered. After the precise controlled time by 100 MHz FPGA, the DUT shortcircuit is switched off by series protection IGBTs. At the same time, the parallel protection is turned on to avoid any unwanted tail current through DUT. The corresponding control time sequences of series, parallel protections and DUT are as shown in Fig. 2 (a). The negative voltage VNEG can speed up the parallel protection, and the Schottky diodes can avoid a current flow from the DUT to the negative voltage. For type 2 short-circuit, the load inductance is required to obtain high current. At first, the series protection is off-state while DUT is turned on. In this case, the DUT conducts current determined by the load inductance. Then, the series protection is turned on and triggered an on-state short-circuit to DUT. Finally, short-circuit is ended with series protection turned off and parallel protection turned-on. The corresponding control time sequences of series, parallel protections and DUT are as shown in Fig. 2 (b). a) b) Fig. 2: Time sequences of the NDT signals. a) type 1 short circuit occurred during turn-on; b) type 2 short circuit occurred during conduction state. Preliminary NDT set-up At first, to tune up the simulation tool and validate the adopted approximations, the preliminary NDT set-up intended for short-circuit current up to 6 kA was built. It includes a series protection made up of two parallel 3300V 3000A IGBT modules, a parallel protection made up of two parallel 3300V, 2400A IGBT modules, the load inductance Lload, DC link capacitance CDC consisting of five parallel capacitors, a high voltage power supply VDC, five 170 V 1200 A parallel Schottky diodes, negativevoltage capacitance CNEG consisting of three parallel capacitors with corresponding negative voltage supply VNEG. During the design of the NDT the inductances of the commutation Loop 1 and Loop 2 should be minimized in order to reduce the influence of short-circuit behaviour. First, focus is on Loop 1 which includes four copper busbars (B1 – B4) as presented in Fig. 1. In order to obtain a low inductance, the busbars in which the current flows in the opposite direction are placed close to each other, the distance is just the thickness of the insulation, which is 0.2 mm (Mylar). Two-layer busbars presented in Fig. 3 (b) (c) are used. The bottom layer is the busbar B4 (Fig. 3 (b)) and the top layer includes the busbars B1, B2, and B3 (Fig. 3 (c)). DUT Schottky diodes Capacitors, CDC Series protection (a) Busbar B2 Busbar B1