Roughness characterization in the frequency domain and linewidth roughness mitigation with post-lithography processes

Abstract

A previously developed linewidth roughness analysis technique is used to characterize post-lithography process roughness reduction in the frequency domain. Post-lithography processes are likely to be required to reach the International Technology Roadmap for Semiconductors roughness specifications for the 32-nm and 22-nm technological nodes. The aim of these processes is to reduce 3 linewidth roughness after etch without dramatic changes in critical dimensions. Various techniques are discussed: in-track chemical processes, ion-beam sputtering, and thermal and plasma treatments-each technique manifests a characteristic smoothing, reducing roughness up to 34%. Exploiting roughness mitigation at different frequencies, our target is to determine whether 50% 3 linewidth roughness reduction after etch is feasible.