Roughness characterization in the frequency domain and LWR mitigation with post-litho processes

Abstract

In this paper a previously developed Line Width Roughness (LWR) analysis techniques is used to characterize postlitho process LWR reduction methods in the frequency domain. Post-litho processes are likely to be required to reach the ITRS 3σLWR target for the 32nm and 22nm half pitch technological node. The aim of these lithographic processes is to mitigate the roughness of the resist and ultimately the etched patterns without a dramatic change in Critical Dimensions (CD). Various techniques are discussed: in-track chemical processes, ion beam sputtering, thermal and plasma treatments as dedicated etch-step. Each technique manifests a characteristic smoothing in the frequency domain reducing the LWR up to 35%. Exploiting LWR reduction at the different frequencies, and combining these techniques, our target is to determine whether 50% overall LWR reduction is feasible.