Robust FinFET Memory Circuits with P-Type Data Access Transistors for Higher Integration Density and Reduced Leakage Power

Abstract

A new six transistor (6T) SRAM cell with PMOS access transistors is proposed in this paper for reducing the leakage power consumption while enhancing the data stabilityand the integration densityof FinFET memorycircuits. With the proposed SRAM circuit, the voltage disturbance at the data storage nodes during a read operation is reduced byutilizing PMOS access transistors. The read stabilityis enhanced byup to 62% while reducing the leakage power byup to 22% as compared to a standard tied-gate FinFET SRAM cell with the same size transistors. One gate of each pull-up FinFET of the cross-coupled inverters is permanentlydisabled in order to achieve write-abilitywith minimum sized transistors. The proposed independent-gate FinFET SRAM circuit with P-type data access transistors reduces the idle mode leakage power, the write power, and the cell area byup to 62%, 16.5%, and 25.53%, respectively , as compared to a standard tied-gate FinFET SRAM cell sized for similar data stabilityin a 32 nm FinFET technology .