An independent-gate FinFET SRAM cell for high data stability and enhanced integration density

Abstract

Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. SRAM arrays are also an important source of leakage in today’s high performance microprocessors. A new six transistor (6T) SRAM cell based on independent-gate (IG) FinFET technology is presented in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density. The new IG-FinFET SRAM cell activates only one gate of the data access transistors during a read operation. The disturbance caused by the direct data access mechanism of the standard 6T SRAM cell topology is significantly reduced by dynamically increasing the threshold voltage of the access transistors. All the transistors in the IG-FinFET SRAM cell are sized minimum without producing any data stability concerns. The read static-noise-margin (SNM) of the new circuit is enhanced by up to 2× as compared to the standard tied-gate FinFET SRAM cells. Alternatively, the IG-FinFET SRAM circuit reduces the leakage power and area by up to 51.7% and 10%, respectively, as compared to the standard tied-gate FinFET SRAM circuits sized for comparable data stability in a 32nm FinFET technology.