Review of Circuit Level Leakage Minimization Techniques in CMOS VLSI Circuits

Abstract

ABSTRACTEver increasing demand for portable and battery-operated systems has led to aggressive scaling. While technology scaling facilitates faster and high-performance devices, at the same time it causes excessive power dissipation especially the leakage. Leakage power dissipation is now a dominating component of total power consumption in today's high-performance chip. So there is a tremendous need to limit the power dissipation in high-density chips, which has initiated many innovative techniques to develop in the design of low power circuits and systems. Nano-scaled very large-scale integration (VLSI) chips have ultra-thin gate oxide, very low threshold voltage, and have short channels. Therefore, leakage power dissipation has emerged as the most challenging issue in VLSI circuit and systems. In this paper, we present a general review of the state-of-the-art circuit level leakage minimization techniques since 1995. It also conceptually classifies the different techniques for leakage minimization. Furthermore, a detailed analysis on the effect of technology nodes on leakage and speed has been carried out using a basic complementary metal-oxide-semiconductor (CMOS) gate with SPICE tool. It also verifies for the reliability issues under process, voltage, and temperature variations. This comprehensive study along with the experimental result can be used to choose the most effective technique for minimizing leakage.