Resource Efficient Metering Scheme for Protecting SoC FPGA Device and IPs in IoT Applications

Abstract

Due to the fact that most of the functions in SoC are handled by the intellectual property (IP) blocks, the CPU plays a minimum role in scheduling the functionality of the IP blocks wherever IP reuse is vital in order to increase the performance and to reduce the resource utilization, cost, and power. This paper aims to propose a hardware-based metering scheme to execute the preferred typing mistake IP (IPs) in a specific SoC FPGA and protect both device and IPs from cloning, misuse, and attacks. The metering service emphasizes a license using a hybrid physical unclonable function (PUF) and finite-state machine (FSM), which hold considerable advantages. The enrolment and activation protocol has been used to authenticate, control, and monitor the Internet of Things (IoT) IPs in an SoC FPGA device. The experimental results show that the resource utilization and power consumption are 8% and 1%, respectively, for activating and executing the IoT IP service with an average delay of 6.6 s. The proposed scheme is implemented in 28-nm FPGAs to secure the chip and IPs and is also compared with recent schemes.