Implementation of Arbiter Physical Unclonable Function on the Xilinx System on Chip FPGA

Abstract

In the Electronic industry, Internet of Things (IoT) design engineers face two significant issues related to hardware security in embedded or IoT applications. The first issue is related to Data Security and the second issue is the security of Intellectual Property (IP) used in IC designing. Generally, data security can be achieved by encrypting the data using a secret key. The key must be kept safe and secured because unauthorized users can perform side-channel attacks while extracting the key from that non-volatile memory. Security of IP becomes crucial because attackers may insert Hardware Trojans into IP or Integrated Circuits (IC). The system design engineers can use the Physical Unclonable Functions (PUFs) to secure hardware devices. It takes the aid of the hardware's manufacture variation to generate unique response bits. Field Programming Gate Array (FPGA) serves as the most comprehensive platform for PUF implementation. This study proposes a different approach for creating and implementing the widely used Arbiter PUF (APUF) on System on Chip (SoC). We have designed and implemented a basic APUF on SOC-FPGA. We defined the challenges and solutions to implement APUF on the SOC-FPGA i.e., Zedboard FPGA evaluation board. The entire experiment is carried out at room temperature. We have verified post-implemented simulation to understand the PUF functionalities. The responses generated by the PUF on SDK were nearly perfect.