Abstract
With the scaling of transistor dimensions, thinner gate oxides results in exponential increases in gate tunneling current and static standby power consumption of CMOS circuits is severely affected by the presence of gate tunneling currents. In this paper, a theory gate tunneling current model in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness is presented and the simulation results in BSIM4 model well agree with the model proposed. The characteristics of current source inverter composed are also studied in detail to analyze its behavior and predict the trends of power dissipated with scaled technology nodes in the effects of gate tunneling current.
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