Research and Design of Data Scrambling and Pseudo Random Sequence Sharing Circuit

Abstract

The data transmitted in the JESD204B transceiver should be scrambled, and the data scrambler is based on linear feedback shift registers (LFSR). Moreover, for the problem of complex circuit design inside the JESD204B transceiver, a built-in self-test (BIST) circuit is added to facilitate testing and verification of the transceiver. In the BIST circuit, the test vector is mostly composed of Pseudo Random Binary Sequence (PRBS), and the PRBS Generator (PRSG) is also based on LFSR. Traditionally, the data scrambler and the PRSG are two separate circuits to implement. A design scheme of logic sharing architecture is proposed in this paper, based on the principle and characteristics of data scrambler and PRSG, by sharing registers and XOR gates. The sharing circuit can realize both scrambling the transmitted data and generate PRBS. This design improves the reuse rate of the circuit and reduces the hardware resource consumption of the circuit. Measurements of the sharing circuit are performed by a FPGA development platform, which proves the effectiveness of the proposed sharing circuit.