Abstract
JESD204B high-speed serial interface is widely used in giga-bit-per-second serial data transaction between ADCs and Application Specific Integrated Circuits (ASIC). According to the complex characteristics of JESD204B system structure, this paper proposed a built-in self-test (BIST) circuits for JESD204B system. By adding Pseudo Random Binary Sequence (PRBS) generator and checker in the critical path, the function of the key module can be verified easily. Moreover, two optional loop-back paths are added in the JESD204B system, which can connected the transmission link and receiving link directly, and makes the test more flexible and effective at the same time. On one hand, the proposed BIST circuits are verified under a FPGA development platform. On the other hand, a 10-Gbps JESD204B transceiver chip with the proposed BIST circuits is fabricated with a 55-nm CMOS process. Both of them proved that the proposed BIST circuits are effective.
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