Abstract
A reliable method for reducing the stacking faults (SFs) is demonstrated on the 3C-SiC (001) surface. It is a practical method based on Monte Carlo (MC) simulations of SF propagation during 3C-SiC epitaxial growth, which showed that introducing some discontinuity on the (001) surface enhanced SF reduction. The method is implemented by patterning on the 3C-SiC (001) surface and subsequent homo-epitaxial growth, and this sufficiently reduced the SF density to less than 400 cm-1. A yield of 97.4 % was estimated for a device-ready area of 10 mm2 by statistical measurements of SF density on the entire epitaxial layer surface.
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