Abstract
This paper compares very-low-voltage (VLV) testing and quiescent power supply current (IDDQ) testing for amorphous silicon thin-film transistor (a-Si TFT) NMOS digital circuits. As many as 140 circuits-under-test (CUT) of two different design styles are implemented in 8 μm a-Si TFT technology on the glass substrate. All CUT are tested both at nominal voltage (10 V) and very low voltage (7 V), followed by a 200-second voltage stress at 30 V. Seven unreliable CUT that escaped nominal voltage (NV) testing are successfully caught by VLV testing. The results indicate that VLV testing is more effective than IDDQ testing to screen out unreliable a-Si TFT circuits. This study suggests that VLV testing is a non-destructive and economic alternative to burn-in for a-Si TFT circuits.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
