Reliability and PVT simulation of FinFET circuits using Cadence Virtuoso

Abstract

Electronics devices faces different environmental condition, manufacturing problems, and mishandling issues cause variations which alters the performance parameters of complementary metal-oxide-semiconductor (CMOS) devices. Future of electronic industry belongs to multi-gate transistors because the impact of the short channel effect on CMOS transistors degrades the circuit performance. Aggressive scaling of CMOS elevates the impact of propagation delay, power dissipation, and various performance parameters. To overcome the problems of CMOS scaling researchers find an alternative multi-gate transistor which is acknowledged as fin field effect transistor (FinFET). FinFET provides better short channel effects (SCEs) control, minimum power dissipation, and superior electrostatic control over the channel as compared to CMOS technology. Although FinFET is the suitable candidate to replace CMOS, the impact of aging and process, voltage, and temperature (PVT) variations is not eliminated from FinFET transistor. In this paper, we designed and simulated different FinFET circuits to check the impact of PVT variations and reliability using the Cadence virtuosos’ tool. We performed reliability simulation and PVT simulation in the Cadence Virtuosos tool with the help of predictive technology model multi-gate (PTM MG) FinFET model files.