Abstract

Fin Field Effect Transistor (FinFET) shows a great potential in scalability and manufacturability as a promising candidate in nanoscale complementary metal-oxide-semiconductor (CMOS) technologies. The structure of FinFET provides superior electrical control over the channel conduction, thus it has attracted widespread interest from researchers in both academia and industry. However, aggressively scaling down of channel dimensions, mainly the channel length, will degrade the overall performance due to detrimental short channel effects (SCEs). This study aims to design an optimal nano-dimensional channel of FinFET on the basis of electrical characteristics and constituent semiconductor materials (Si, GaAs, Ge, and InAs) to overcome issues regarding the shrinking of dimensions and ensure the best performance of FinFETs. This objective has been achieved by proposing a new scaling factor, K, to simultaneously shrink the physical scaling limits of channel dimensions for various FinFETs without degrading their performance. A simulation-based comprehensive comparative study depending on four (4) variable parameters (length, width, oxide thickness of the channel, and scaling factor) was carried out. The influence of changing channel dimensions on the performance of each type of FinFET was evaluated according to four electrical characteristics: (i) ON-state/OFF-state current (I ON/ I OFF ) ratio, (ii) subthreshold swing (SS), (iii) threshold voltage, and (iv) drain-induced barrier lowering. The well-known multi-gate field-effect transistor (MuGFET) simulation tool for nanoscale MuGFET structure was utilized to conduct experimental simulations under the considered conditions. The obtained simulation results showed that the optimal channel dimensions for the best performance of all considered FinFET types were achieved at a minimal scaling factor K = 0.125 with 5 nm length, 2.5 nm width, and 0.625 nm oxide thickness of the channel.

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