Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

Abstract

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O2/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.