Effect of Gate Dielectric on Performance of Polysilicon thin Film Transistors

Abstract

AbstractThe effect of gate dielectric on the electrical characteristics of n-channel polysilicon thin film transistors was investigated. The following insulators were studied: silicon dioxide grown by wet oxidation, silicon dioxide deposited by plasma enhanced chemical vapor deposition (PECVD) and nitrogen-rich silicon nitride deposited by PECVD. It was observed that the effective electron mobility in TFTs having a deposited dielectric, either silicon nitride or silicon dioxide was higher than that measured in devices with grown silicon dioxide. The TFT leakage current was found to be lowest in devices with PECVD silicon nitride. Devices with deposited dielectrics did not degrade after a positive gate bias stress. However, reduction of the threshold voltage was observed in devices with PECVD silicon nitride, when they were subjected to a negative gate bias stress.