Reducing specific on-resistance for a trench SOI LDMOS with L-shaped P/N pillars

Abstract

To reduce specific on-resistance (Ron,sp) of power devices, a novel SOI (silicon-on-insulator) trench gate LDMOS with heavily doping L-shaped P/N pillars and vertical dual-trench-gates is proposed in this paper, and its physical mechanism and electrical performance are investigated by numerical simulation. The L-shaped P-pillar raises the optimal doping impurity concentration of the drift region (Nd) remarkably from 1.7 × 1015 cm−3 to 1.25 × 1016 cm−3 by causing assistant depletion effect for drift region, hence a lower specific on-resistance (Ron,sp) with a 3.6 mΩ·cm2 is achieved. Meanwhile, the voltage capacity of the new structure is improved resulting from two new electric-field peaks produced by L-shaped P/N pillars. Consequently, a much lower Ron,sp and a higher breakdown voltage (BV) are achieved by the proposed structure. Simulated results show that the Ron,sp, BV, and Baliga’s figure of merit (FOM, FOM = BV2/Ron,sp) for the new structure are improved by 84.3%, 31.4%, and 991%, respectively, in comparison with the conventional trench LDMOS.