Abstract
Semiconductor technology scaling makes NAND flash memory subject to continuous raw storage reliability degradation, leading to the demand for more and more powerful error correction codes. This inevitable trend makes conventional BCH code increasingly inadequate, and iterative coding solutions such as low-density parity-check (LDPC) codes become very natural alternative options. However, fine-grained soft-decision memory sensing must be used in order to fully leverage the strong error correction capability of LDPC codes, which results in significant data access latency overhead. This article presents a simple design technique that can reduce such latency overhead. The key is to cohesively exploit the NAND flash memory wear-out dynamics and impact of LDPC code structure on decoding performance. Based upon detailed memory device modeling and ASIC design, we carried out simulations to demonstrate the potential effectiveness of this design method and evaluate the involved trade-offs.
Highlights
Solid-state storage systems based upon NAND flash memory technology must use error correction code (ECC) to ensure the system-level data storage integrity
We present a simple design technique to reduce the latency overhead caused by the use of low-density parity-check (LDPC) codes
Experiments Based upon the above NAND flash memory device model, we carried out simulations to compare the errorcorrection performance between soft-decision and harddecision LDPC code decoding and demonstrate the effectiveness of the proposed adaptive design method
Summary
Solid-state storage systems based upon NAND flash memory technology must use error correction code (ECC) to ensure the system-level data storage integrity. As the semiconductor industry continues to push the technology scaling envelope and pursue aggressive use of multi-level per cell storage, raw storage reliability of NAND flash memory continues to degrade, which quickly makes current design practice inadequate and naturally demands more powerful ECCs. As the semiconductor industry continues to push the technology scaling envelope and pursue aggressive use of multi-level per cell storage, raw storage reliability of NAND flash memory continues to degrade, which quickly makes current design practice inadequate and naturally demands more powerful ECCs Because of their well-proven error correction capability with reasonably low decoding complexity and recent success in hard disk drives, low-density parity-check (LDPC) codes [2,3] have attracted many attentions because of their applications in NAND flash memory.
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