Reduced-Latency and Area-Efficient Architecture for FPGA-Based Stochastic LDPC Decoders

Ghania Zerari,Abderrezak Guessoum

doi:10.14569/ijacsa.2017.080707

Abstract

This paper introduces a new field programmable gate array (FPGA) based stochastic low-density parity-check (LDPC) decoding process, to implement fully parallel LDPC-decoders. The proposed technique is designed to optimize the FPGA logic utilisation and to decrease the decoding latency. In order to reduce the complexity, the variable node (VN) output saturated-counter is removed and each VN internal memory is mapped only in one slice distributed RAM. Furthermore, an efficient VN initialization, using the channel input probability, is performed to improve the decoder convergence, without requiring additional resources. The Xilinx FPGA implementation shows that the proposed decoding approach reaches high performance along with reduction of logic utilisation, even for short codes. As a result, for a (200, 100) regular codes, a 57% reduction of the average decoding cycles is attained with an important bit error rate improvement, at Eb/N0 = 5.5dB. Additionally, a significant hardware reduction is achieved.

Highlights

The need for increasing the throughput of modern communication systems capacity, for optical and wireless networks, requires high performance error correcting code
It has been demonstrated that the enlargement of the variable node (VN) internal memories size increases the low-density parity-check (LDPC) stochastic decoding converges [10]-[11]
To confirm the improvement of the new design, a medium (1024, 512) and short (200, 100) LDPC codes are implemented on Xilinx Virtex-6 VLX240T field programmable gate array (FPGA) device, with various methods

Summary

INTRODUCTION

The need for increasing the throughput of modern communication systems capacity, for optical and wireless networks, requires high performance error correcting code. It has been shown that the higher throughput is achieved by the fully parallel decoding solutions; they enlarged the hardware complexity. To overcome this drawback, several reduced-complexity and stochastic LDPC decoding algorithms are developed [6]-[8]. For additional silicon area reduction, diverse LDPC stochastic based decoding architectures and strategies are proposed. An area-efficient architecture for ASIC-Based stochastic LDPC decoder can’t systematically produces an efficient FPGA logic utilisation. This paper introduces a new and powerful field programmable gate array (FPGA) based stochastic Low-Density ParityCheck (LDPC) decoding process, to implement fully parallel LDPC-decoders.

LDPC STOCHASTIC DECODERS

Check to variable node

PROPOSED LDPC STOCHASTIC STRUCTURE

IMPLEMENTATION RESULTS AND PERFORMANCE

CONCLUSION