Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates

Abstract

Reconfigurable field effect transistors (RFETs) are an emerging technology platform that offers the possibility to merge <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${n}$ </tex-math></inline-formula> -type and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${p}$ </tex-math></inline-formula> -type functionalities in a single device. From the circuit perspective, this feature enables layout camouflaged designs by realizing polymorphic logic gates with dynamically reconfigurable functions. In this work, mixed-mode simulations employing a technology computer-aided design (TCAD) model of RFETs with three gates are presented. Three different designs for reconfigurable NAND/NOR logic gates are analyzed in order to optimize the equalization of both operational modes delay traces. Moreover, work function fluctuations arising from process variations are considered to prove that their inevitable presence can be exploited to further increase the level of obfuscation between those modes. Statistical analysis of the results from 100 simulated devices shows effective overlapping of the distribution of the delays extracted at half the value of the drain voltage. Together with a good resilience against supply voltage variations in fault induction attacks schemes, these results suggest how this emerging technology can grow up and evolve to play an interesting role in the field of hardware security.