Electronic Assessment of Novel Arch-Shaped Asymmetrical Reconfigurable Field-Effect Transistor

Abstract

In this article, a novel arch-shaped asymmetrical reconfigurable field-effect transistor (RFET) has been proposed for the first time. By adding an arch-shaped source region in a silicon nanowire, the ON-state saturated current ( ${\mathrm {I}}_{ \mathrm{\scriptscriptstyle ON}}$ ) is found to raise about 6.72 times for the n-type and $5.39\times $ for the p-type, compared with conventional RFET. The tunneling and conduction mechanism is investigated in detail by 3-D technology computer aided design (TCAD) simulations. It is demonstrated that the geometry parameters of the arch-shaped source in our proposed asymmetrical RFET have a significant impact on the tunneling area, tunneling strength, and serial resistance. Moreover, the arch-shaped source is able to reduce the gate capacitance ( ${\mathrm {C}}_{\text {gg}}$ ) as well. The increased ${\mathrm {I}}_{ \mathrm{\scriptscriptstyle ON}}$ and the decreased ${\mathrm {C}}_{\text {gg}}$ lower the propagation delay decreased by 51.9% in basic combination logic applications.