Abstract
LSI trends and technological background allowing the full-scale introduction of SOI (Silicon on Insulator) CMOS are described, the features of SOI CMOS and its effectiveness for achieving low power consumption and high speed of LSIs are summarized, and application examples are presented. In connection with the future prospects of SOI CMOS, descriptions of parasitic effects, which are becoming more prominent with scaling, device structures capable of suppressing them, concepts of performance improvement under the future trend of supply voltage lowering, and the necessary technology, are discussed. © 2000 Scripta Technica, Electron Comm Jpn Pt 2, 83(10): 24–34, 2000
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