Abstract
Ternary logic has some distinct advantage over binary logic. In this paper we propose a synthesis approach for ternary reversible circuits using ternary reversible gates. Our method takes a boolean function as input. The input is provided as .pla file. The .pla file is first converted into ternary logic function, which can be represented as permutation. The gate library used for synthesis is Ternary Not, Ternary Toffoli and Ternary Toffoli+ (NT ,TT ,TT+). The proposed constructive method, generates 3-cycles from the permutation, and then each 3-cycle is mapped to (NT ,TT ,TT+) gate library. Experimental results show that the method generates lesser number of gates for some circuits compared to previously reported works.
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