Reactive Ion Etching of WPR for Via Formation in High Density 3-D Chip Stacking Technology

Abstract

Three-dimensional (3-D) chip stacking technology, for a large number of devices in a single die area on a system board, has recently emerged as an extent of Moore’s law. Chip-to-chip interconnection is a key issue for 3-D chip staking, and through silicon via (TSV) is suggested as one possible solution to realize better electrical performance. In the mean time, an inter-chip dielectric plays the role of an insulating material that provides better electrical properties of fast signal transmission and less crosstalk. In addition, the inter-chip dielectric serves as an underfill that provides mechanical reliability, including coefficient of thermal expansion (CTE), moisture absorption, heat dissipation, and etc. In this paper, we report reactive ion etching of WPR, a relatively new insulating material, to form a high-aspect-ratio dielectric via-hole for applications in high-density 3-D chip staking technology. We have found that the etch rate is directly proportional to the RF power and that a significant amount of interaction exists between the chamber pressure and the gas ratio of CH4 to O2. Physical etching induced by fluorine helps anisotropic etching, but polymeric etch residuals may remain.