RapidLayout: Fast Hard Block Placement of FPGA-optimized Systolic Arrays Using Evolutionary Algorithm

Abstract

Evolutionary algorithms can outperform conventional placement algorithms such as simulated annealing, analytical placement, and manual placement on runtime, wirelength, pipelining cost, and clock frequency when mapping hard block intensive designs such as systolic arrays on Xilinx UltraScale+ FPGAs. For certain hard-block intensive designs, the commercial-grade Xilinx Vivado CAD tool cannot provide legal routing solutions without tedious manual placement constraints. Instead, we formulate hard block placement as a multi-objective optimization problem that targets wirelength squared and bounding box size. We build an end-to-end placement-and-routing flow called RapidLayout using the Xilinx RapidWright framework. RapidLayout runs 5–6 \( \times \) faster than Vivado with manual constraints and eliminates the weeks-long effort to manually generate placement constraints. RapidLayout enables transfer learning from similar devices and bootstrapping from much smaller devices. Transfer learning in the UltraScale+ family achieves 11–14 \( \times \) shorter runtime and bootstrapping from a 97% smaller device delivers 2.1–3.2 \( \times \) faster optimizations. RapidLayout outperforms (1) a tuned simulated annealer by 2.7–30.8 \( \times \) in runtime while achieving similar quality of results, (2) VPR by 1.5 \( \times \) in runtime, 1.9–2.4 \( \times \) in wirelength, and 3–4 \( \times \) in bounding box size, while also (3) beating the analytical placer UTPlaceF by 9.3 \( \times \) in runtime, 1.8–2.2 \( \times \) in wirelength, and 2–2.7 \( \times \) in bounding box size.