Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain

Abstract

This paper proposes a placement algorithm using analytical placement (AP) and low-temperature simulated annealing (SA) for mixed-grained reconfigurable architecture (MGRA) with dedicated carry chains. The target MGRAs are assumed to have fine-grained blocks with dedicated carry chains to implement high-speed adders/subtracters and coarse-grained blocks to implement complicated arithmetic operations. Although this mixed-grained architecture is expected to enhance the performance of the implemented application circuit, placement becomes problematic because of the inherent placement constraints. For example, some logic blocks have many connections to others and constraints such as these cause simple pair-swap-based SA to converge to a local optimum. The proposed algorithm uses AP to determine an initial placement for SA. The AP explores an appropriate placement of coarse-grained blocks and adders/subtracters consisting of fine-grained blocks and dedicated carry chains. On the other hand, SA is mainly used to determine optimal placement of the remaining fine-grained blocks. The evaluations show that the proposed algorithm reduces the placement cost, critical path delay, and runtime by 18.4%, 6.0%, and 67.6% on average, respectively, over the versatile place and route (VPR) approach. The benchmark includes circuits consisting of only fine-grained logic. Hence, the proposed algorithm is expected to improve the placement quality for a wide range of application circuits.