Abstract

In both ULSI and VLSI the sizes of MOS transistors have been scaled to submicron and micron gate widths such that the requisite dimensions of the gate dielectric films are typically less than 200 A. Rapid thermal processing (RTP) of thin dielectrics has therefore become a topic of great interest for achieving good electrical properties with a reduced thermal budget for the manufacture of these circuits. This has had particular impact in manufacturing memory devices where very high packing density is required. For example, dynamic random-access memories (DRAMs) [1], electrically programmable readonly memory (EPROM) [2], electrically erasable programmable read-only memory (EEPROM) [3], and greater than 64-Mbit random-access memory (RAM). The presence of oxide charge is clearly demonstrated by the threshold voltage shifts and leakage currents. These effects become more pronounced as the gate oxide thickness decreases and the gate capacitance increases. In EEPROMs Fowler-Nordheim (FN) tunneling current, which is used to charge and discharge the gate of the memory cell, can slowly degrade the gate dielectric properties through trapped charges in the gate dielectric. The resultant shift in the threshold voltage and increase in the leakage current reduces the time a bit of information is held in the memory cell, thus leading to electrical failure of the device. A second advantage of RTP is incorporating nitrogen into the dielectric to reduce boron penetration which occurs when p+-polysilicon is used in the fabrication of the gate electrode in p-channel MOSFETs.

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