Racetrack memory: A storage class memory based on current controlled magnetic domain wall motion

Abstract

Racetrack Memory promises a novel storage-class memory with the low cost per bit of magnetic disk drives but the high performance and reliability of conventional solid state memories[1]. Unlike conventional memories, the fundamental concept of Racetrack Memory (RM) is to store multiple data bits — as many as 10 to 100 bits- p er access point, rather than the typical single bit per transistor. This is accomplished in Racetrack Memory by storing data bits in the for m of domain walls in m agnetic nanowires which are oriented either parallel to the surf ace or perpendicular to th e surface of a silicon wafer (see Figure 1). These distinct structures form “horizontal” and “vertical” Racetrack Memories. Conventional CMOS devices and circuits are used to provide for the creation and manipulation of the domain walls in the magnetic nanowires or “racetracks”. The domain walls are shifted along the nanowires using nano-second long current pulses via th e transfer of s pin angular momentum from the spin polarized curren t generated in the magnetic nanowire racetracks[2].