RaceCheck: A Race Logic Audit Program For SoC Designs

Abstract

This paper describes RaceCheck, a new verification program that audits System-on-Chip (SoC) designs for race logic design errors. The unique features of RaceCheck are: it can perform both static and dynamic analysis to reveal hard-to-detect race logic, and it makes use of SoC designs' structural and timing information to suppress false violations. The static race logic analysis is testbench independent, and can be used in all stages of a SoC development. The dynamic race logic analysis uses an event-driven simulation kernel to execute a SoC operations, and reports the exact times, locations and frequency of occurrences of all detected race logic in the design. RaceCheck complements traditional design verification tools to aid users achieve 100 % functional coverage of their new SoC products and time-to-market