Quick Design of a Superjunction Considering Charge Imbalance Due to Process Variations

Abstract

The breakdown voltage, ${V}_{{\text {BR}}}$ , of a superjunction whose pillar parameters, namely doping, length, and width, are optimized to yield the least specific ON-resistance, ${R}_{{\text {ONSP}}}$ , for the specified ${V}_{{\text {BR}}}$ , falls drastically for even small charge imbalances. Hence, a structure fabricated with these target parameter values often has a ${V} _{{\text {BR}}}$ much lower than specified due to the charge imbalance caused by random process variations. We give an analytical solution for alternate target parameter values which yield the specified ${V}_{{\text {BR}}}$ in spite of process variations, with minimum sacrifice in ${R} _{{\text {ONSP}}}$ . The solution is obtained by the method of Lagrange multipliers and a simple equation for the breakdown field versus charge imbalance. It is validated by TCAD simulation. It can either be approximated to a closed-form or can yield the target parameter values accurately with just a few iterations. Apart from eliminating the tedious iterations of prior design methods, our solution provides two new insights: when compared with an optimum balanced device, a device optimized considering typical charge imbalance has significantly lower pillar doping but almost the same pillar length and width; the breakdown field of a balanced device is a power law function of the pillar length alone. Although illustrated for 4H-SiC structures with ${V}_{{\text {BR,target}}}$ of 1–10 kV, our solution should work for any semiconductor after material specific changes.