Quantitative study of metal–oxide semiconductor field effect transistor damage induced by scanning tunneling microscope lithography

Abstract

The channel areas of n-channel silicon metal–oxide semiconductor field effect transistor (MOSFET) devices have been patterned with an air-operated scanning tunneling microscope (STM) and processed to completion. Gate oxide thickness modulations greater than 80 Å have been achieved with this technique. The impact of the STM process step on the silicon/insulator interface has been characterized with two-level charge pumping. The number of interface traps attributable to the STM lithography process is roughly 7×1010/cm2 eV. Additionally, transistor parameters from the STM FETs are compared with those from virgin FETs to assess any possible leakage current and mobility degradation induced by the STM process.