P-WLCSP: 6-Side Protected WLCSP

Abstract

The first silicon demonstration of 300mm P-WLCSP was introduced in 2021 at the 54th International Symposium on Microelectronics. This paper reports further developments and new test results for this low cost WLCSP approach to fully protected CSP. The paper briefly summarizes the evolution of protected CSP technology evolution as an introduction for a more extensive discussion of P-WLCSP. With the advent of bumped die new IC packages evolved: for low IO WLCSP (wafer level chip scale package) and for high IO FC (flip chip) CBGA (ceramic ball grid array) and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), packages were built on the wafer with no active side protection evolving to 1 sided protection from a package built on the wafer2 which transition to redistribution PSB (passivation stress buffer)3, PSBs were used on FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability performance evolved to CSP (non WF) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. Fully protected die CSP (without substrates or leadframes) was initially implemented with processes such as M-series utilizing a FO (fan out) process.5 To obtain higher reliability 6-sided die protection afforded by M-series type processes require die reconstitution, expensive tapes, molding operations required in a FO process that can be eliminated in a WLCSP protected FI process. American Semiconductor’s Semiconductor-on-Polymerâ?¢ (SoPâ?¢) 300mm FleX-TM P-WLCSP is an advanced packaging process optimized for protected fan-in. P-WLSCP ultra-thin fully protected chips will be shown from a wafer level process. Process development progress and test results will be presented.