Abstract
The test pattern generator produces test vectors that are applied to the tested circuit during pseudo-random testing of combinational circuits. The nature of the generator thus directly influences the fault coverage achieved. In this paper we discuss the influence of the type of pseudo-random pattern generator on stuck-at fault coverage. Linear feedback shift registers (LFSRs) are mostly used as test pattern generators, and the generating polynomial is primitive to ensure the maximum period. We have shown that it is not necessary to use primitive polynomials, and moreover that their using is even undesirable in most cases. This fact is documented by statistical graphs. The necessity of the proper choice of a generating polynomial and an LFSR seed is shown here, by designing a mixed-mode BIST for the ISCAS benchmarks.An alternative to LFSRs are cellular automata (CA). We study the effectiveness of CA when used as pseudo-random pattern generators. The observations are documented by statistical results.
Highlights
The complexity of present-day VLSI devices has risen to millions of gates, and the chips are becoming untestable by standard manufacture external ATE (Automated Test Equipment) testers
First we show that the testability and the fault coverage achieved by a certain number of pseudo-random test vectors strictly depend on the tested circuit
The distribution of weights on the individual pseudo-random pattern generator (PRPG) outputs is shown for all cases, together with the fault coverage curves obtained by the PRPGs
Summary
The complexity of present-day VLSI devices has risen to millions of gates, and the chips are becoming untestable by standard manufacture external ATE (Automated Test Equipment) testers. We introduce statistics on the stuck-at fault coverages for the ISCAS [10, 11] and ITC’99 benchmarks [21], using different PRPGs. The influence of the PRPG on the total BIST area overhead is shown for the column-matching method [7, 13, 14], since this method enables high scalability, and the effects of the generator type and test lengths can be demonstrated here very well. An n-bit (n-stage) LFSR is a linear sequential circuit consisting of D flip-flops and XOR gates generating code words (patterns) of a cyclic code. We have performed extensive experiments on the standard ISCAS benchmarks, both combinational benchmarks [10] and full-scan versions of sequential benchmarks [11], to determine the fault coverage achieved by a pseudo-random test sequence generated by a PRPG. We demonstrate the effect of the generator type on the stuck-at fault coverage, and show that the simplest LFSR is sufficient for most of applications
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
