Abstract
A VLSI-compatible approach for vector-matrix multipliers consisting of a two-dimensional array of analog multiplier circuits with the weight matrix values capacitively stored as analog voltages is described. The performances of several MOSFET analog multiplier circuits, including the triode, differential pair, Gilbert, and modified Gilbert multiplier circuits, are evaluated. The weight retention characteristics of the capacitive storage approach are evaluated as a function of temperature with effective weight decay rates of 30 and 0.6 mV/s at room temperature measured for the single- and double-capacitor storage arrangements, respectively. The design approach for a 32*32 programmable vector-matrix multiplier circuit with an analog serial-to-parallel multiplexer for the input vector and an analog parallel-to-serial multiplexer for the output vector is described. An architecture for cascading the 32*32 vector-matrix multiplier circuits to implement multilevel artificial neural networks is described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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