Abstract
Low-frequency analog integrated circuit design is a challenging task considering the threat imposed by flicker noise. This paper presents design and analysis of analog multiplier circuit using p-channel MOS transistor, in contrast to the traditional approach of designing using n-channel MOS transistor. Exhaustive simulation using SCL 180 nm process technology is performed. This includes dc, transient, and harmonics analysis. We derive compact analytical model of various performance parameters and compare it with simulation results. Good matching between the two has been obtained. The application of multiplier circuit for demodulation purpose is shown.
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