Cascadable 32*32 vector-matrix multiplier for artificial neural networks

Abstract

Summary form only given, as follows. A cascadable 32*32 vector-matrix multiplier circuit implemented with a new eight-transistor programmable analog multiplier cell is described. The analog multiplier circuit performs a full four-quadrant analog-analog multiply operation. A hybrid digital-analog approach is utilized for implementing the vector-matrix multiplier. The analog weight storage is provided by the capacitive storage of an analog voltage at the gate of MOSFET transistors and the analog weights are refreshed from weight values stored in a digital memory using a digital-to-analog converter. The 32*32 vector-matrix multiplier utilizes an analog series-to-parallel multiplexer for the input vector and an analog parallel-to-series multiplexer for the output vector to reduce the number of I/O pads. Architectures for cascading the 32*32 vector-matrix multipliers to implement multilevel artificial neural networks and large vector-matrix multipliers are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>