Transition faults detection in bit parallel multipliers over GF(2 m )

Abstract

In this article, a C-testable design for detecting transition faults in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m) is discussed. For 100 percent transition fault coverage, the proposed technique requires only 10 vectors, irrespective of multiplier size, at the cost of 6 percent extra hardware. The proposed constant test vectors which are sufficient to detect both the transition and stuck-at faults in the multiplier circuits can be derived directly without any requirement of an ATPG tool. As the GF(2m) multipliers have found critical applications in public key cryptography and need secure internal testing, a Built-in Self-Test (BIST) circuit may be used for generating test patterns internally. This will obviate the need of having three extra pins for the control inputs and also provides public-key security in cryptography. Area and delay of the testable circuit are analyzed using Synopsys® tools with 0.18µ CMOS technology library from UMC.