Processing Challenges of CMOS Integration of Finfets with All-Last Gate Stacks

Abstract

FinFETs with 20nm BEOL with one generation improvement in performance and power efficiency has announced for mass production by leading IC companies. The processing details, however, have never been reported. In this talk, processing challenges of CMOS integration of FinFETs with all-last gate stacks is presented based on our recent results. Special processing issues in Fin and the replacement gate (RMG) formation, RMG filling with high-k/metal gate and self-aligned contact (SAC) module will be discussed. It is found that the etching of dummy gate of FinFETs behaves differently from that in planar MOSFETs. Thick enough dummy SiO2 is needed for protecting the Fin from plasma damage during dummy gate etch. Wet removal of dummy SiO2 in gate area faces also the risk of Fin damage, due to galvanic corrosion, and thus prefers to a thin SiO2 for control of the wet processing window. It is shown that TaN coverage of the channel area is important in single dielectric dual metal gate stack, where a p-FET stack is first deposited in both n- and p-area, and then the top work function metals in n-area will be removed before n-FET metal deposition. ALD TaN is studied systematically for the the etch stopper application. It is found that the largest issue in the CMOS integration of the FinFETS is n-work function metal deposition. Poor TiAl coverage induces large Vt variation. ALD TiAl could be a good solution for n-work function metal deposition. Filling of the RMG, which has extremely large AR in FinFETs, and SAC is a big challenge. A systematic study of ALD W shows that its advantage in properties such as adhesion, conformality and good constraint by TiN barrier enables good fill of the gaps. Electrical characterizations of the FinFETs are presented in order to show the impact of the above issues to device behavior variation.