Process Tolerant Design Using Thermal and Power-Supply Tolerance in Pipeline Based Circuits

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This paper describes a thermal and power-supply tolerant design methodology for pipeline based circuits. It is shown that by making the circuit more tolerant to VDD and temperature (T) instability, even in the presence of process variations, a yield loss reduction is achieved. The goal is to improve signal integrity in the presence of power-supply voltage (VDD) and/or temperature (T) variations, without degrading circuit performance. By using time borrowing techniques, data integrity loss is avoided, and circuit tolerance to VDD and/or temperature variations is enhanced. The methodology is based on a dynamic delay buffer (DDB) block, used to sense VDD/T variations and to induce dynamic clock skews driving a limited subset of key memory elements. Monte Carlo simulations are used to demonstrate that the proposed methodology still holds, even in the presence of process variations.