Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations

Abstract

A new methodology is proposed to increase the robustness of pipeline-based circuits. The goal is to improve signal integrity in the presence of power-supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) and/or temperature (T) variations, without degrading circuit performance. In the proposed methodology, we dynamically control the instant of data capture (the clock edge trigger) in key memory cells, according to local V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> and/or T variations. This way, data integrity loss is avoided, and circuit tolerance to power supply and/or temperature variations is enhanced. The methodology is based on a dynamic delay buffer (DDB) block, used to sense V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> /T variations and to induce dynamic clock skews driving a limited subset of memory elements. Experimental results based on SPICE simulations for 2 sequential circuits are used to demonstrate that careful design may lead to improvements on circuit tolerance to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> and/or T variations.